Systems implemented on highly integrated semiconductor circuits are increasingly important, particularly in producing circuits used to implement battery-operated devices, such as cell phones, portable computers, such as laptops, notebooks and PDAs, wireless e-mail terminals, MP3 audio and video players, portable wireless web browsers, and the like. Sometimes these integrated circuits are referred to as “SOIC” (for “systems on an integrated circuit”) or “SOC” (for “systems on a chip”) devices. SOC devices increasingly include analog circuitry as a portion of an integrated function that also includes a large digital portion, for example, a microprocessor, DSP, RISC processor, or another large digital portion, often including on-board data storage. As is known in the art, SOCs have portions that operate as part of a system, for example, a portion of the integrated circuit may implement a so-called analog front end or AFE, the analog portion of a wireless receiver or a transmitter. Sensors such as anti-locking braking sensors, pressure sensors, temperature sensors, and other input sensors are often implemented using a large analog circuit and an analog to digital converter circuit that is then coupled to an on-board processing unit that is formed from digital logic circuitry. These highly integrated circuits require a variety of on-board supply voltages. Often these on-board supply voltages are created as “stepped down” voltages from a higher off board supply voltage, although “step up” circuits are also known. Many portable devices now being produced are powered by a battery supply, which creates a first supply voltage, and various on-board voltages are needed within the integrated circuit to power different functions. Typically these batteries are rechargeable so that even when recharging, the voltage that operates the circuit is taken from the DC battery supply.
In the prior art, a regulated supply voltage output is often provided using an LDO or “low drop out” voltage regulator circuit. As is well known in the art, the LDO relies upon the control of a power FET, operated in a continuous-time fashion, coupled between the input voltage and a lower output voltage. Feedback is used to compare a reference voltage taken across a resistor at the output to a regulated reference voltage. If the output voltage is rising above the desired output (e.g., the power demanded by the load, in the form of load current, is dropping), the bias voltage to the gate of the FET is raised (if it is a PMOS device) or lowered (if it is an NMOS device). Conversely, if the output voltage is dropping below the desired output, the bias voltage to the gate of the FET is lowered (if it is a PMOS devise) or raised (if it is an NMOS devise) to provide additional current to the load so that the output voltage rises to the desired level. Thus, the LDO is a linear circuit.
The efficiency of the LDO circuits of the prior art is higher with a higher output voltage (relative to the input voltage) but can be quite low with lowered output voltages. In applications where the output voltage of the LDO is low, for example, less than 1V with a 1.8V input supply, the efficiency may be quite low, which means an increase in wasted power. This inefficiency leads to shorter battery life, or shorter battery operating time between charges for rechargeable devices, for example. Present circuits may often operate at even lower operating voltages and this inefficiency becomes more problematic as operating voltages for integrated circuits decrease.
Another prior art DC-to-DC converter solution is to use an off-chip switching regulator with off-chip components, or an on-chip controller with off-chip components. Switching regulators are known to be able to achieve increased efficiencies at lower output voltages than LDO circuits. As integration increases and the size of the devices is reduced, the use of off-chip regulators, and/or of off-chip components, becomes undesirable for several reasons. Further, the use of switching regulators with typical switching frequencies in wireless or cellular device applications can create tone frequencies and noise problems that are unacceptable.
FIG. 1 depicts an example of a simplified circuit diagram of a prior art synchronous switching regulator circuit or buck converter. The circuit uses a series inductor and a capacitor to provide an output voltage Vout at a terminal with the output taken across the capacitor. The buck converter replaces the power device used in classical LDOs with a series combination of a power switch and an inductor. By switching the power switch on and off at a given frequency with a given duty cycle, the inductor maintains an average current equal to the current needed by the load. Further, with the aid of a feedback control circuit, output voltage Vout can be maintained at a regulated level while providing the load with the needed current by manipulating the duty cycle of the switching or the switching frequency itself. However, the switching of the power device results in a regulated average output voltage with voltage ripples around the regulated level.
The implementation of a fully integrated on-chip switching regulator, such as that of FIG. 1, requires using on-chip components including a capacitor and an inductor, as well as the switching circuitry. In an exemplary circuit, at a typical semiconductor technology process node of 65 nanometers, a capacitor of 400 pF and an inductor of 80 nH was calculated, with the switching circuitry, to require a silicon area of roughly about 0.85 mm2. Of this area, the on-chip inductor requires approximately 0.8 mm. In simulation, with a fixed switching frequency and a Pulse Width Modulation (PWM) control scheme, the circuit can be shown to have substantially increased efficiency in producing output voltages ranging from 0.6V to 1V from a 1.8V input supply voltage, when compared to a typical LDO regulator providing the same output voltages. At 1V, a preliminary study shows the switching regulator to have an efficiency of roughly 70% with an output load current of 10 milliamps and a supply voltage of 1.8V. At an output voltage of 0.7V, with an output load current of 7 milliamps, the efficiency drops to around 60%, but the circuit is still substantially more efficient than an LDO at the same output load current and output voltage.
Silicon area is the biggest problem in implementing the fully integrated synchronous buck converter of FIG. 1 with on-chip capacitors and inductor, and most of the area is due to the 80 nH on-chip inductor. The same design but using a 10 nH inductor instead of an 80 nH inductor has been evaluated. In this case, the area for the inductor is reduced to 0.09 mm2 in the same exemplary 65 nanometer semiconductor process technology. This circuit, however, has two significant problems that make it impractical for use as a regulator. First, the reduction in the inductor value results in a larger current ripple in the inductor, and thus a larger output voltage ripple. Second, a significant efficiency loss is observed due to operating the inductor in discontinuous conduction mode, which is a direct unavoidable result of reducing the inductor value while at the same time maintaining the fixed switching frequency and the PWM control scheme. Using the smaller inductor resulted in an efficiency drop from about 70% with the 80 nH inductor to about 25.5% with the 10 nH inductor, which is even worse than a linear regulator (LDO) in the same output voltage and load current conditions.
A study was also made using the synchronous rectifier or buck converter described above with the smaller on-chip 10 nH inductor in discontinuous conduction mode but using a Pulse Frequency Modulation (PFM) control scheme instead of the PWM control scheme. Using this technique improved the efficiency, and the ripple obtained was similar to an LDO. The efficiency of such an approach at a 1V output voltage with a 10 milliamp load current was 61%. The efficiency at a 0.7V output voltage with a 7 milliamp load current was 60%. However the use of a PFM control scheme is not practical for many applications because the varying frequency of the switching circuitry produces an unpredictable ripple voltage spectrum at the output that is a function of the load current, and thus cannot be easily filtered. In wireless applications in particular, or in other noise-sensitive applications, using a PFM control scheme is highly undesirable due to its unpredictability.
DC-DC converters arranged without inductors are also known in the prior art. A switched capacitor circuit may be used to provide a stepped-up, stepped-down, or unity gain configuration DC-DC converter. In a switched capacitor circuit, a “flying” or charge transfer capacitor is alternatively switched between being coupled to an input voltage (typically a battery or other DC voltage) and to the load, while a holding or load capacitor is used to maintain the output voltage at the load. The discharge of the two capacitors at the output voltage terminal will provide output load current. The load or holding capacitor is discharged along with the flying capacitor during the “gain” portion of the cycle, and the charge transfer or flying capacitor is charged by the input supply during the “common” portion of the cycle. Switches are used to reconfigure the circuit in a clocked arrangement. Typically, two non-overlapping clocks are applied to the circuit to drive the switches.
FIG. 4 depicts a simple circuit diagram of a typical switched capacitor circuit. The particular function of the circuit in FIG. 4 is to step-down a voltage VBAT, a DC supply voltage, to an output voltage Vout. By using ratios for the capacitors C1 (having a value 2CB) and CL, the output voltage Vout may be modified. As is known to those skilled in the art, the gain may be determined by different arrangements of the capacitors C1 and CL, for example, the circuit in FIG. 4 will give a stepped-down output voltage of Vin/2. A paper, authored by one of the inventors of the present application, entitled “Voltage Scalable Switched Capacitor DC-DC Converter for Ultra-Low Power On-Chip Applications” by Yogesh K. Ramadass and Anantha P. Chandrakasan, published in Proceedings of the IEEE Power Electronics Specialists Conference, pp. 2353-2359, February 2007, (hereinafter “Ramadass”), which is herein incorporated by reference, describes a variety of capacitor topologies to provide output voltages from a single supply while using a PFM scheme to regulate the output voltage.
The switched capacitor circuit is operated by clocking the switches labeled SW1A, SW1B, SW2A and SW2B with non-overlapping continuous waveforms or clocks Φ1 and Φ2. In this manner, the capacitor C1, the charge transfer or “flying” capacitor, is alternatively charged by the battery or discharged into the load, and the current is transferred to the load by the transfer capacitor CL. Simple digital circuitry is used to build the non-overlapping clocks Φ1 and Φ2 from a clock signal, and typical frequencies may vary from 10 kHz to 100 MHz.
FIGS. 5a and 5b depict representative simplified circuitry illustrating the two phases of operation of the switched capacitor circuit of FIG. 4. In FIG. 5a, the phase 1 clock Φ1 is active. This places the 1/2 gain switched capacitor circuit of FIG. 4 in “common” mode, wherein the battery is coupled to the circuit and provides current to charge the flying capacitor. During this phase, switches SW1A and SW1B in FIG. 4 are closed while switches SW2A and SW2B in FIG. 4 are open. Then, as illustrated in FIG. 5b, in the second phase of operation, the phase 2 clock Φ2 is high or active, switches SW2A and SW2B in FIG. 4 are closed, and switches SW1A and SW1B in FIG. 4 are open. In this configuration, the flying capacitor C1 of FIG. 4 is coupled to the load in parallel with the load capacitor CL and the load current discharges the capacitors. This phase is sometimes called the “gain” operation. As the current is discharged from the capacitors C1 and CL by the load coupled to the Vout terminal (see FIG. 4), the circuit will have to again receive energy from the DC supply voltage VBAT. By constantly cycling the clocks Φ1 and Φ2, the switched capacitor circuit of FIG. 4 will provide a DC output voltage (the “no load” voltage) of voltage level VBAT/2.
As is also well known in the art, and as further described by Ramadass, the use of different capacitor topologies in the switched capacitor circuit can provide a wide range of gain ratios, including stepped-up and stepped-down ratios. FIG. 6 depicts a simplified illustration of a switched capacitor circuit that provides a gain of 2/3. In FIG. 6 two capacitors C2 and C3 are provided in the transfer capacitor stage with corresponding switches.
During the phase of operation when clock Φ1 is high, switches SW1A, SW1B, SW1C and SW1D are closed. An examination of the circuit of FIG. 6 then reveals that in this “common” phase, capacitors C2 and C3 having values CB are both coupled between the input VBAT and the output terminal Vout, and so are receiving charge from the battery or other DC voltage source.
During the second phase of operation, when the clock Φ1 is low, the clock Φ2 is high (again, non-overlapping with Φ1. Switches SW2A, SW2B and SW2C are closed. Examination of the circuit then reveals that capacitors C2 and C3 are now connected in series between the ground terminal and the output voltage Vout, and the series combination is in parallel with capacitor CL, which is discharging to the load. Thus, the output voltage Vout is now 2/3 of VBAT, instead of 1/2, as in the circuit of FIG. 4.
To provide a practical regulated supply voltage, the output voltage Vout must be regulated. Feedback or hysteretic control circuitry is typically used to provide the control loop for the DC-DC converter function. Because the output voltage Vout depends on how many cycles there are (pulse frequency) and the length of time the clocks Φ1 and Φ2 are active (pulse width), modulation schemes are known in the prior art using voltage monitoring circuitry (typically a sense resistor at the output provides a proportional monitoring voltage) and op amp comparators or other comparator circuitry to detect when more, or less, current is needed to maintain the output voltage Vout at a desired DC level. When the comparator circuitry determines more current is needed by the load (output voltage Vout is falling), the control circuitry will either increase the switching frequency (in PFM mode) or increase the amount of time the charge transfer capacitor C1 is charged by the VBAT by modulating the pulse width of the clocks Φ1 and Φ2 (PWM) until the output voltage Vout increases. When the load is demanding less current, the output voltage Vout will rise, and the control circuitry will provide correspondingly less energy from the VBAT by reducing the switching frequency (in PFM mode) or by reducing the pulse width (in PWM mode) in order to maintain the output voltage Vout within a desired range.
DC-DC switched capacitor circuits using PFM or PWM control schemes are practical solutions for many applications. The efficiency of these circuits can be improved using various known schemes including “pulse skipping” for no load or light load conditions or “stand by” or “sleep” modes of operation for remaining conditions. Some known approaches also use gain hopping. Since the efficiency of the switched capacitor circuit increases when the “no load” voltage is very close to the desired output voltage Vout, changing the gain can improve efficiency. For example, duty cycle control is described in a paper entitled “Duty-Cycle Control Boosts DC-DC Converters,” by Cheong et al., IEEE Circuits and Devices Magazine, vol. 9, pp. 36-37, March 1993. However, the use of PFM control schemes creates tones or spurs in the output voltage Vout that are not predictable, making effective filtering of these tones impracticable. Thus, the use of this kind of control to achieve voltage regulation in a switched capacitor DC-DC converter is not preferable for many applications where the unpredictable tone frequency is not acceptable, for example, in certain analog, wireless, cellular or other transmitting and receiving technologies where the tone noise would make operation of the circuitry coupled to the output voltage Vout in the load impossible.
Another approach to regulate output voltage Vout of switched capacitor DC-DC converters uses fixed frequency approaches. U.S. Pat. No. 6,995,995, issued Feb. 7, 2006 to Zeng, et al., describes the use of segmented switches to regulate the output voltage Vout provided during the charging or gain phase of the clock cycle. In this segmented switch mode, the size of the switches (the current path) is modulated while the switching frequency is left constant. While these approaches will not have the same tone or noise unpredictability problems of the PFM control scheme, other problems arise. By using PWM control schemes or segmented switch modes (changing the current supplied to the capacitors by changing switch sizes to regulate the output voltage), these approaches rely on a fixed switching frequency regulation scheme. However, the loss mechanisms associated with switched capacitor circuits do not scale with the load power in these schemes. Also, effective output regulation in response to wide variations in load power cannot be obtained using switched capacitor DC converters regulated with these approaches.
A need thus exists for an area-efficient and cost-effective solution to the problem of providing a regulated DC output voltage from a DC input supply voltage with high efficiency even at low regulated voltages or no load conditions. The circuit must be practical to integrate on the same integrated circuit with other digital and analog circuitry, be silicon area efficient, and must provide small voltage ripple. The use of a fixed frequency of operation is needed to produce tone spurs or noise only at predictable, filterable frequencies in the output so as to be compatible with analog, cellular and wireless applications, while maintaining the output voltage within a narrow regulation variance over a wide range of load power demand conditions.